1. Field of the Invention
The present invention relates generally to semiconductor fabrication. More specifically, the present invention relates to material deposition on a semiconductor wafer.
2. Description of the Related Art
In the fabrication of semiconductor devices such as integrated circuits, memory cells, and the like, a series of manufacturing operations are performed to define features on semiconductor wafers. The semiconductor wafers include integrated circuit devices in the form of multi-level structures defined on a silicon substrate. At a substrate level, transistor devices with diffusion regions are formed. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define a desired integrated circuit device. Also, patterned conductive layers are insulated from other conductive layers by dielectric materials.
The series of manufacturing operations for defining features on the semiconductor wafers can include many processes such as adding, patterning, etching, removing, and polishing, among others, various material layers. Due to the intricate nature of the features defined on the semiconductor wafers, it is necessary to perform each process in a precise manner. For example, it is often desirable to deposit a material on a surface of the wafer such that the material conforms uniformly to a topography of the surface of the wafer.
FIG. 1A is an illustration showing a cross-section view of the wafer surface following a non-uniform material deposition, in accordance with the prior art. The wafer surface is defined to have features 101 and 102 which form a topography across the wafer surface. The topography is characterized by surfaces that are substantially parallel to the wafer and surfaces that are substantially perpendicular to the wafer. Additionally, some features (e.g., feature 102) may be skewed such that their surfaces are neither parallel nor perpendicular to the wafer.
Prior art methods of material deposition using physical vapor deposition techniques tend to deposit greater amounts of material on feature surfaces having greater exposure to a material source region 111 from which the material is deposited. In general, the material source region 111 is represented by the region above the wafer. Therefore, since feature surfaces that are substantially parallel to the wafer have greater exposure to the material source region 111, these feature surfaces tend to accumulate greater amounts of deposited material. For example, with respect to FIG. 1A, a thickness 107 of a deposited material 103 is larger than a thickness 105, wherein the thicknesses 107 and 105 are deposited on feature surfaces that are substantially parallel and perpendicular, respectively, to the wafer. Additionally, in some instances the non-uniformities in material deposition can be significant enough to cause discontinuities in the material being deposited. For example, a discontinuity 109 is shown at a location underlying an overhang of the skewed feature 102. In certain applications, it is more desirable to have a uniform thickness of the material deposited over each feature surface regardless of the feature surface orientation. Also, it is generally not acceptable to have discontinuities present in a deposited material layer. Thus, non-uniform material deposition caused by variations in surface exposure to the material source region 111 can be problematic.
FIGS. 1B-1 through 1B-4 are illustrations showing a material deposition sequence leading to void formation, in accordance with the prior art. FIG. 1B-1 shows a wafer surface having features 101 prior to deposition of the material 103. The features 101 define a topography of the wafer surface. In some instances, the features may represent high-aspect ratio features wherein the ratio of the feature's vertical dimension to its lateral dimension is greater than 2 or 3 to 1.
FIG. 1B-2 shows a beginning stage of a material deposition process intended to fill a space between the adjacent features 101 with the material 103. As previously discussed with respect to FIG. 1A, prior art material deposition methods tend to result in deposited material layers having non-uniform thicknesses. The thickness 107 of the deposited material 103 is larger than the thickness 105, wherein the thicknesses 107 and 105 are deposited on feature 101 surfaces that are substantially parallel and perpendicular, respectively, to the wafer.
FIG. 1B-3 shows a later stage of the material deposition process intended to fill the space between the adjacent features 101 with the material 103. Due to the non-uniform material deposition, the feature 101 surfaces that are substantially parallel to the wafer have accumulated a greater thickness of the material 103 than the surfaces that are substantially perpendicular to the wafer. Furthermore, as the lateral deposition continues and the lateral distance diminishes, it becomes more difficult for reactants to reach the lower region and further reduces the deposition rate in these regions.
FIG. 1B-4 shows the final result of the material deposition process intended to fill the space between the adjacent features 101 with the material 103. Due to the non-uniform material deposition, the deposited material on each of the substantially parallel feature 101 surfaces ultimately reaches a thickness at which a bridge is formed between adjacent features. The bridge results in formation of a void, or keyhole, 113 within the space between the adjacent features 101. Thus, non-uniformities in material deposition can lead to unsatisfactory material deposition results.
In view of the foregoing, there is a need for an apparatus and a method to uniformly deposit a material over a wafer surface.